This invention is related to integrated circuit memories, and in particular to one-time programmable memories, often referred to as OTP Memory. Nonvolatile memory retains stored data when power is removed, and is used in many different applications. As system-on-chip (SoC) technology becomes more prevalent in consumer electronics and industrial applications, embedded nonvolatile memories have become more common. Embedded memory is included on the same semiconductor die with other non-memory circuitry, typically logic circuitry.
An embedded memory can be used for various purposes, for example, providing chip IDs, analog trimming, yield enhancement, code storage, etc. It is advantageous if the embedded memory does not require added masks or other process modifications to a standard CMOS process flow. Flash NAND or NOR memory using multiple polysilicon layers is not compatible with standard CMOS processing. Gate dielectric based anti-fuse memory increasingly has become the choice of SoC chip designers because it can be included on the chip using standard CMOS processes, and it is reliable and secure.
Gate dielectric anti-fuse based memory can be broadly categorized into two types, depending upon its operating principle. One type is cross-point memory consisting of a single capacitor at each grid point. The second type has more than two access lines for each cell in the memory array. A typical example is a storage capacitor or transistor coupled in series with a selection device such as a transistor or diode.
Cross-point memory arrays are advantageous due to their compact layout and simple decoding. As a result, embedded OTP memories of the first type can be about eight times smaller than those of the second type. One cross-point memory is described in commonly assigned U.S. patent application Ser. No. 14/250,267 filed Apr. 10, 2014, and entitled “One-Time Programmable Memory and Method for Making the Same.”
One challenge to OTP memory is reducing the amount of power consumed by such memories, e.g. for battery powered applications, or other applications where low power consumption is advantageous. In OTP memories relying upon oxide breakdown, after breakdown the memory typically has a relatively low oxide resistance, for example, between 10 K ohms and 100 K ohms. Typically, for a memory array there is a resistance distribution where some cells are seen with the resistance at the lowest end of the range (10 K Ohms or possibly lower). These low resistance cells inherently consume significant power during the sensing operation.
In reading data from such memories, the content of each addressed cell is read producing either a ‘0’ (not programmed) or a ‘1’ (programmed, oxide is broken-down). The result is output from the sensing circuit as a bit of data. There is a need, especially in low power systems, to sense the state of the OTP memory cell utilizing low total power dissipation, despite the OTP memory cell having a low resistance and potentially consuming high power were traditional sensing means used.